1. Field of the Invention
The present invention relates to a bus system, and more particularly, to a bus system suitable for a system-on-chip and a path decision method therefor.
2. Description of the Related Art
Conventional bus systems have been developed as systems outside chips mounted on a board. However, due to advances in semiconductor manufacturing technology, the development and use of system-on-chips, in which a majority of functional blocks are implemented on a single chip, is gradually increasing.
Bus systems outside chips are being applied to system-on-chips in an early stage without modification. Since such a system-on-chip has smaller wire characteristics, i.e., inductance L, resistance R, and capacitance C, than those of a gate, a high-speed system can be made using the structure of a conventional bus system.
As chips such as very deep sub-micron (VDSM) chips and ultra deep sub-micron (UDSM) chips having very narrow wires for connecting functional blocks are manufactured on a large scale with the development of micro processing technology, the time taken for a signal to pass through the functional blocks is reduced. However, a wire delay that was ignored in the past becomes more important than a cell delay and it is difficult to predict the influence which the wire delay exerts on system performance at an early stage of a design. Accordingly, when a conventional bus system designed without an in depth consideration of a wire delay is applied to a system-on-chip as it is, the entire system performance may be degraded. In the case of a system-on-chip, the entire chip performance heavily depends on the efficiency of a bus structure taking charge of data transmission, so bus systems for system-on-chips have been actively researched.